Electronics And Communication Engineering
Mr RAJESH KANUGANTI. Has Submitted his Ph.D Thesis in SSUTMS-BHOPAL in 2023.
He completed M.Tech from Andhra University in 2009
He completed B.Tech from JNTU, HYDERABAD in 2005.
He is author of VLSI CHIP DESIGN by LAKSHMI PUBLICATIONS CHENNAI with
ISBN: 978-933-87950-66-5.
He has total teaching, research and administrative experience of 17 years.
His research interests include thin VLSI, MEMS and gas sensors.
Research
- Journal publications: 09
- International Conferences: 04
Achievements
- FET Qualified in 2011,
- Received Best Faculty Award in A.Y 2019-2020
- Professional memberships: IAENG,
- Administrative roles executed:
- PG Course co-coordinator
- Training and placement officer
- Project co-coordinator
- IQAC Member
- Editor reputed journals.
